News
Our paper titled “ReBERT: LLM for Gate-Level to Word-Level Reverse Engineering” has been nominated for best paper in DATE’2025. Congratulations to first author Lizi Zhang and thanks to our industry collaborator Dr. Rasit Topaloglu. This paper discusses an effective way to encode a a gate-level circuit in a Hardware Description Language to enable reverse engineering to the higher bit-level using Large Language Models. We combine three embedding schemes to encode circuit information to best be understood by the BERT model. This includes a novel tree-based positional embedding scheme to encode the position of each gate within the graph structure of a circuit as a token sequence.
Congratulations to Lizi for winning a $1000 travel award to present his paper at MLCAD’24.
Paper accepted in IEEE/ACM Symposium on Machine Learning for CAD on effective use of neural networks for automatic test pattern generation (ATPG) in VLSI. Neural networks are used to reduce the number of backtracks when searching the decision tree of test patterns, and reduce the runtime of ATPG. Our results show neural networks are not effective if applied for backtracing in circuit nodes which are too close to, or too far away from, the inputs. We also propose a look-up technique to reuse previously-computed inferences to significantly accelerate the runtime. The neural network itself should not be too complex because of the associated inference overhead, and overall objective to reduce the runtime of ATPG. Congratulations to first (and only student) author Lizi Zhang. He will present his work in Snowbird Utah in September 2024. A version of this paper also appeared in Int’l Workshop on Logic & Synthesis in June 2024.
Congratulations to Robert and Lizi for winning multiple travel awards (over $3500) to present their research at DAC, SmartComp and MLSys (Young Professional Symposium) at San Francisco, Japan, and Santa Clara.