New Paper

Paper accepted in IEEE/ACM Symposium on Machine Learning for CAD on effective use of neural networks for automatic test pattern generation (ATPG) in VLSI. Neural networks are used to reduce the number of backtracks when searching the decision tree of test patterns, and reduce the runtime of ATPG. Our results show neural networks are not effective if applied for backtracing in circuit nodes which are too close to, or too far away from, the inputs. We also propose a look-up technique to reuse previously-computed inferences to significantly accelerate the runtime. The neural network itself should not be too complex because of the associated inference overhead, and overall objective to reduce the runtime of ATPG. Congratulations to first (and only student) author Lizi Zhang. He will present his work in Snowbird Utah in September 2024. A version of this paper also appeared in Int’l Workshop on Logic & Synthesis in June 2024.